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VHDL IP: AD7303

Summary
This VHDL macro is intended for interface (say) PicoBlaze with the 8-bit DAC AD7303 from Analog Devices or compatible ones. Such device is included in Digilent AIO1 peripheral board sold by Digilent

Chip Description

The AD7303 is an 2-channel 8-bit DAC with a SPI interface. Rather than use a complete, general SPI master transceiver, I developed an specific (''ad hoc'') interface logic which is extremely simple and easy to use from PicoBlaze or some system else.

The interface moves two 8-bit samples in 68 system clock cycles so the maximum DAC data rate @50MHz is 50 x 10^6 / 68 = 735.29 kHz for each channel. The predefined configuration for AD7303 (It is possible to use other config modifying the VHDL code, it's no possible use different configurations once the design is implemented) is:

  • the two DAC channels enabled
  • collect data from the shift register instead from input register
  • set the internal reference (Vdd/2)

Ports and Usage

The macro has the following ports:

Port DIR Type Description
reset Input signal Asynchronous reset
clk Input signal Clock signal. Must be lower than 60MHz because ''sclk'' freq. is a half of the ''clk'' freq. and the AD7303 admit a ''sclk'' of 30MHz at maximum
wr Input signal Chip enable (write signal). Start the tx operation, ''rdy'' goes low until the macro has finished the tx of two samples (L and R).
XL_wr Input signal Chip enable signal for the XL register
XR_wr Input signal Chip enable signal for the XR register
XL Input 8-bit bus Register that stores the "left" sample (AD7303 is a 2-channel DAC)
XR Input 8-bit bus Register that stores the "right" sample (AD7303 is a 2-channel DAC)
rdy Output signal Ready signal, while the macro is busy, this signal is 0
int_rdy Output signal Rise one clock cycle pulse when ''rdy'' goes 1 (use it to interrupt PicoBlaze for example)
sclk Output signal SPI serial clock signal
din Output signal SPI serial data signal
sync Output signal SPI chip select signal

Put data samples on ''XL'' and ''XR'' ports and assert ''XL_wr'' and ''XR_wr'' until the next ''clk'' rising edge, then assert ''wr'' signal until the ''clk'' rising edge. At this moment ''rdy'' goes 0, the sample will be transferred to DAC in 68 clock (''clk'') cycles. Wait ''rdy'' signal to be 1 again, this notifies you that the transmission has finished. See the cronogram below.

Block Diagram And Control State Machine

The figure depicted below shows the RTL block diagram of the circuit. All sequential blocks share the same asyncronous reset and clock signals. The control finite state machine (FSM) has 9 states, there are 6 control signals for datapath. The 4-bits up counter serves to greatly simply the FSM's graph.

Datapath

Control

Statersselsyncosr_ceosr_ldctr_cesclk
e000 - 1 0 0 0 0
e010 0 1 1 1 0 0
e020 0 0 0 0 1 0
e030 0 0 1 0 0 1
ee 0 - 1 - - 0 0
e040 1 1 1 1 0 0
e050 1 0 0 0 1 0
e060 1 0 1 0 0 1
e070 - 0 0 0 1 0

The FSM has the following graph, state after reset is e0, the control signals in each state are shown in the table. The signals printed in green are registered because random effects on this signals could cause a malfunctioning of entire system (AD7823 expects inputs free of spurious transitions)

Synthesis Report

    Device xc3s400-4ft256

    slice=30
    ff=45
    lut=42
    iob=26
    gclk=1
    mfreq=233.91MHz
  

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References

Today is Monday, 27-Mar-2017 04:28:17 EDT.
This page was last modified on Monday, 02-Jan-2017 10:01:25 EST.