-- Hi Emacs, this is -*- mode: vhdl; -*- -------------------------------------------------------------------------------- -- VHDL Test Bench for ad7303.vhd macro -- -- 2007 Javier Valcarce García, javier.valcarce@gmail.com -------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- The MIT License -- -- Copyright (c) 2007 Javier Valcarce García -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ad7303_test_vhd is end ad7303_test_vhd; architecture behavior of ad7303_test_vhd is -- Component Declaration for the Unit Under Test (UUT) component ad7303 port( reset : in std_logic; clk : in std_logic; wr : in std_logic; XL_wr : in std_logic; XR_wr : in std_logic; XL : in std_logic_vector(7 downto 0); XR : in std_logic_vector(7 downto 0); rdy : out std_logic; int_rdy : out std_logic; sclk : out std_logic; din : out std_logic; sync : out std_logic ); end component; --Inputs signal reset : std_logic := '0'; signal clk : std_logic := '0'; signal wr : std_logic := '0'; signal XL_wr : std_logic := '0'; signal XR_wr : std_logic := '0'; signal XL : std_logic_vector(7 downto 0) := (others => '0'); signal XR : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal rdy : std_logic; signal int_rdy : std_logic; signal sclk : std_logic; signal din : std_logic; signal sync : std_logic; begin -- Instantiate the Unit Under Test (UUT) uut : ad7303 port map( reset => reset, clk => clk, wr => wr, XL_wr => XL_wr, XR_wr => XR_wr, XL => XL, XR => XR, rdy => rdy, int_rdy => int_rdy, sclk => sclk, din => din, sync => sync ); -- Initial reset rs : process begin reset <= '1'; wait for 50 ns; reset <= '0'; wait; end process; -- clock ck : process begin clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process; tb : process begin -- Wait 100 ns for global reset to finish wait for 100 ns; XL <= "11110000"; XR <= "10101010"; XL_wr <= '1'; XR_wr <= '1'; wait for 40 ns; wr <= '1'; wait for 60 ns; -- Place stimulus here wait; -- will wait forever end process; end;