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VHDL IP: PS2

Summary
This VHDL macro is a PS2 controller to connect a PS2 keyboard, mouse, etc. It is only a receiver, i.e., receives data only sent by PS device (device → host).

Block description

Port DIR Type Description
reset I signal Asynchronous reset
clk I signal Clock signal, must be x4 faster at least than kbclk
kbdata I signal PS2 serial data
kbclk I signal PS2 data clock (~15 kHz)
newdata O signal One clk cycle pulse, to raise an interrupt in PicoBlaze for example
do O 8-bit bus Byte sent by PS2 device

When a new data is available in do, a pulse (one clock cycle pulse) is sent by newdata signal notifying the host circuit to transfer the octet to a FIFO buffer or something else. System clock clk must be faster (x4 or more) than kbclk (kbclk is about 15 kHz).

Synthesis report

Device Utilization
Devicexc3s400-4ft256
Slices28
FFs44
LUTs31
IOBs13
GCLK1
Maximun clock frequency178.859 MHz

Simulation

Cronogram in ModelSim for transmision of character 0x0F from keyboard to host

Chronogram here

Download

Files:

References

  • The PS/2 Mouse/Keyboard Protocol
  • "Diseño digital con lógica programable", 1º edición, Luis Jacobo Álvarez Ruiz de Ojeda, Tórculo Edicions, ISBN 84-8408-301-2

Today is Monday, 27-Mar-2017 04:29:26 EDT.
This page was last modified on Monday, 02-Jan-2017 10:01:25 EST.