-- Hi Emacs, this is -*- mode: vhdl; -*-
----------------------------------------------------------------------------------------------------
-- Interface for AD7823 (1-ch 8-bit 200kSPS Analog To Digital Converter)
-- 
-- 2007 Javier Valcarce García, javier.valcarce@gmail.com
-- $Id$
--
----------------------------------------------------------------------------------------------------
-- The MIT License
--
-- Copyright (c) 2007 Javier Valcarce García
-- 
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity ad7823_test_vhd is
end ad7823_test_vhd;

architecture behavior of ad7823_test_vhd is

  -- Component Declaration for the Unit Under Test (UUT)
  component ad7823
    port(
      reset    : in  std_logic;
      clk      : in  std_logic;
      clk10MHz : in  std_logic;
      start    : in  std_logic;
      di       : in  std_logic;
      eoc      : out std_logic;
      do       : out std_logic_vector(7 downto 0);
      sclk     : out std_logic;
      convst   : out std_logic
      );
  end component;

  --Inputs
  signal reset    : std_logic := '0';
  signal clk      : std_logic := '0';
  signal clk10MHz : std_logic := '0';
  signal start    : std_logic := '0';
  signal di       : std_logic := '0';

  --Outputs
  signal eoc    : std_logic;
  signal do     : std_logic_vector(7 downto 0);
  signal sclk   : std_logic;
  signal convst : std_logic;

begin

  -- Instantiate the Unit Under Test (UUT)
  uut : ad7823 port map(
    reset    => reset,
    clk      => clk,
    clk10MHz => clk10MHz,
    start    => start,
    eoc      => eoc,
    do       => do,
    di       => di,
    sclk     => sclk,
    convst   => convst
    );

  -- 50MHz clock 
  ck1 : process
  begin
    clk <= '0';
    wait for 20 ns;
    clk <= '1';
    wait for 20 ns;
  end process;

  -- 10MHz clock
  ck2 : process
  begin
    clk10MHz <= '0';
    wait for 50 ns;
    clk10MHz <= '1';
    wait for 50 ns;
  end process;


  tb : process
  begin
    reset <= '1';
    wait for 50 ns;
    reset <= '0';
    wait for 50 ns;

    -- Place stimulus here
    start <= '1';
    wait for 50 ns;
    start <= '0';

    wait;                               -- will wait forever
  end process;

end;